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Home > Electronic Components > Nichia Jupiter LED Lamp Teardown and Technology Analysis
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Nichia Jupiter LED Lamp Teardown and Technology Analysis

  • Published by: MuAnalysis
  • Published: January, 2009
  • Format : PDF /
  • Delivery: E-Mail within 1-2 business days
  • Product ID: 81213
Price: USD 3000
Format: PDF

Tel : +1-860-674-8796

Description

Abstract

Summary

The low-profile package is very straightforward in concept and design, and uses materials which are typical in the high-power LED industry. As the LED die substrate is electrically insulating, there is no back-side contact to the die. Three bond wires for anode and three for cathode connect to the die front. Die attach is by an unfilled and probably insulating adhesive of unusually thin and apparently well controlled glue line thickness, probably to minimize thermal resistance to the heat sink.

The included protection device is a silicon Zener diode providing ESD and possibly overstress protection.

The fluorescent medium coating of the blue LED die is unusually thick, but has a correspondingly low density of Gd/YAG fluorescent particles.

The die is an InGaN/GaN hetero-structure with a multiple quantum well (MQW) active region, on a sapphire substrate. A thick In-rich InGaN layer serves as the pside (top) current spreader layer. The MQW (also InGaN/GaN) is between GaN layers, below the InGaN /GaN interface. Interdigitated p-side (surface) and n-side (recessed) contact fingers handle current distribution.

The optical concept is conventional, with upward emission dominating and side emission directed upward by a silvered conical reflector in the package. There is no anti-waveguiding feature incorporated. There is no device-level back-side reflector either, but back-side reflectance is aided by the transparent substrate and die attach material and the silvered heat slug.


Table of Contents

Table of Contents

1. Product Identification

2. External Appearance and Principal Dimensions

3. Package General Description

  • Substrate structure and material
  • Phosphor and encapsulation
  • Die configuration and attach
  • Electrical protection
  • Table of package parameters

4. Semiconductor Die

  • Materials, dimensions, and singulation
  • Appearance
    • Lower level contact
    • Upper level contact
  • Epi-stack
  • Table of die process parameters

5. Summary

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